Question about clock + PLL

Depends on the nature of the said warnings. The 100 MHz clock may be simply too fast for your design.

The warning was: Critical Warning: Timing requirements for slow timing model timing analysis were not met. See Report window for details.

PLLs inside FPGAs are normally happy if they have their clock input dedicated to them only i.e. not driving anything else. That is what you did when you changed your design.

Thank you very much, i will take that on consideration on my next designs. Very usefull information!

I didn't understand your above description at first look. ALthough the PLL output is locked to the input clock, there's additional delay skew between in- and output clock.

It was my impression that the general course of action was to use a 1/1 divider for one of the pll outputs if you want to use the base clock frequency. At the very basic level, there is no guarantee that the pll is exactly synchronous in phase with the input clock. This might not be a problem if you are clocking completely independent modules that have no interaction (and therefore you might be safe in ignoring the warnings), but as kaz pointed out, there are other factors to consider, like the input requirements of the pll.

This is probably (OP didn't provide too much details) an issue of hold timing violations due to transfers between the original clock and the PLL output one.