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Altera_Forum
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16 years ago

Question about clock + PLL

Hi, probably that is going to be a very noob question but... I am using PLL on a Clyclone II, and i was clocking some blocks directly from my 50Mhz oscilator input and some other blocks from a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

PLLs inside FPGAs are normally happy if they have their clock input dedicated to them only i.e. not driving anything else. That is what you did when you changed your design.