Question about clock + PLL

The warning was: Critical Warning: Timing requirements for slow timing model timing analysis were not met. See Report window for details.

But if 100Mhz is too fast for my design, why the critical warning and all other time warning just disapeared after i used the 1:1 output of PLL instead of using the input directly? Actualy it does not generate a warning even at 200Mhz.... (the 200Mhz is just used for sample purposes on a UART receiver). And that 200Mhz had the same use of the 100Mhz one... And the paths that were generating the warning were the 50Mhz ones and not 100Mhz...

I think i was kind confusing at my description.. was that understandable?

Thank you!