Question about clock + PLL

It was my impression that the general course of action was to use a 1/1 divider for one of the pll outputs if you want to use the base clock frequency. At the very basic level, there is no guarantee that the pll is exactly synchronous in phase with the input clock. This might not be a problem if you are clocking completely independent modules that have no interaction (and therefore you might be safe in ignoring the warnings), but as kaz pointed out, there are other factors to consider, like the input requirements of the pll.