New ContributorQuartus Programmer no longer detects FPGA/CPLD
I have a fully operational v10.1 Arria II GX (EP2AGX125EF35I5ES) project complete with SOPC, Serial Lite II and DDR. It has a Cypress S29 CFI_1G and a MAX II (EPM2210F324I5) for configuration. The Navy vendor uses PFL in the CPLD to only program the CFI_1G. They created their own VHDL to configure the FPGA. I have for months been trying to update the v10.1 project to v17.1 but I cannot because the FPGA NSTATUS constantly asserts during configuration. I even created identical v10.1 and v17.1 Bare Bones projects with no IP or processes and no GTX or DDR pins assigned and the FPGA still will not configure. There is no issue with the v10.1 bare bones project during configuration. I think that there is something going on when converting the SOF to POF with v16.1/v17.1 and even v18.1. The v17.1 bare bones project asserts NSTATUS at POF address 0x21054 and I cannot figure it out.
To make a long story short, yesterday, I decided to try and make a v17.1 standalone PFL_CONFIG project. I assigned the clock (50MHz), reset_n and all pins to the CFI_1G and FPGA. I flashed the CPLD and power-cycled. It did not work. However, now Quartus Programmer (any version) does not recognize any device on the JTAG chain. The JTAG signals go to both the CPLD and FPGA. I did try stopping and re-starting the JTAG Server. What could have happened and what should I do?
