Quartus Programmer no longer detects FPGA/CPLD

I think my only solution is to replace the MAX II. It is controlling the FPGA_RST_N and I failed to assign this CPLD pin when I made this bare bones PFL Config project. There is a 10K pull-up and I tried manually putting 3.3V on it but there was no change. So as of now I am waiting for the CPLD's and stencil to get ordered. I will post the result when I get the items hopefully within a few weeks.

However, I am currently working the issue on another unit. I am now thinking that my issue could be related to how the vendor's FPGA configuration components is addressing the CFI. I have found that there is a 13-byte offset in the POF data between a v10.1 bare bones (no processes, logic or IP) POF and a v17.1 bare bones POF. Using Hex Editor to view the POF's and observing CFG_D I can see where in the POF that NSTATUS is asserting. I am currently working on this.