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Altera_Forum
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9 years ago

Quartus Error (13066): Illegal directional connection from the pin (inout)

Hello all, I've posted this question to VHDL board, please forgive me if you've seen it there. Just thought it could be Quartus related so repost it here again. I'm using Quartus 16 lite to c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Hi, Tricky,

Thanks for pointing it out. I solved it now.

Here is my code, put it below for people who're using the development module and keeping the old pin definition. Hope it can help.

regards,

Yu 

.................
signal   iBusData_IN,iBusData_OUT, iData : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal   tmp_iBusData_IN,tmp_iBusData_OUT: STD_LOGIC_VECTOR (7 DOWNTO 0);
...................
		Process (in_aclr, FT2232_clk)
		begin
			if in_aclr = '0' then 
				tmp_iBusData_IN <= (others => '0');
				tmp_iBusData_OUT <= (others => '0');
			elsif rising_edge(FT2232_clk) then
				tmp_iBusData_IN <= GPIO_0(15 downto 8);
				tmp_iBusData_OUT <= FIFO_q;
			end if;
		end process;
----------	Arrange range to fitGPIO_0(8 to 15)
Reverse_bits:
		for i in iBusData_IN'range generate
			iBusData_IN(i) <= tmp_iBusData_IN (iBusData_IN'high -i);
			iBusData_OUT(i)<= tmp_iBusData_OUT (iBusData_IN'high -i);
		end generate;
			 
		GPIO_0(15 downto 8) <= iBusData_OUT when nOE ='1' else (others => 'Z');