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Altera_Forum
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16 years ago

PWM signal problem

Hello,

could someone explain a strange problem with PW signal. The signal period is 30 ms, and PW triggers in between 0.7 and 2,2 ms.

But, I'v got a problem since the moment the signal rise it falls down again just like in the following picture.

http://img396.imageshack.us/img396/7549/pulse.png

I wonder if I have to assign special characteristics to the output pin in Quartus pin assignment sheet. I think VHDL code is ok. Perhaps some silly thing I overlooked.

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  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    So the high pass time constant is in a 100 us Range. When I asked for the waveform scaling, I also referred to the voltage (level of wide noisy line and peak-to-peak value.)

    If I understand the trigger level display correct, the base line is around zero and the negative peak is actually below zero. A level, that can never be driven actively by a FPGA I/O that's really connected to this signal. You could pick it up instead from an unconnected trace running directly beneath the driven signal.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    If the probe is known to work correct, you may be probing a wrong pin. check the neighbours too.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    FvM, I think the board is faulty. But one more thing before I finalize my conclusion: what about this signal produced by VHDL single counter and no signals in sensitivity list. The peak to peak is just 10 - 12 mV. Have I done something wrong or do I miss something ?

    http://img128.imageshack.us/img128/2865/pulse3.png
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    It seems to be basically the same issue of a capacitive coupled signal. Because of higher frequency, you see (almost) a square wave now. The problem is neither related to VHDL, sensitivity lists nor FPGAs in particular.

    P.S.: You may want to start by assigning a static DC level ('H' or 'L') to some output pins and trace it with a multimeter. FPGAs have, by the way, a trivial method of disabling all outputs by enabling the global DEV_OE pin in device options without asserting it. You should exclude this option, too. Also supplying no VCCIO to a bank may possibly have similar results.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Daixiwen, batfink, FvM , thank you very much.

    I found the problem. It was a short patch of wire between the board pin and probe. I totally neglected its significiance , very silly me who did not think it can cause such an attenuation.

    Now when I checked the pin directly, the signal is perfect with no noise and with perfect shape.