Forum Discussion
Programming S25FL256 through Cyclone 10 with file from Processor
- 2 years ago
Hi,
signaltap waveform shows that you don't understand Avalon MM timing requirements. We see e.g. mem_read active while mem_ waitrequest is asserted which must never happen.
Imagine that mem_write starts a serial flash cycle with adress and data bits. Waitrequest indicates ongoing serial interface activity, next memory read/write can't happen before waitrequest is release. Similar problems exist with csr interface.
Hi Jcole,
I hope the explanation above by our fellow community members, FvM would address your concern.
Regards,
Fakhrul
Hi Fakhrul,
It does help, I've been trying to use the Generic Serial Flash Interface to send data. Been having some trouble with the core in simulation, I've been writing to the addresses listed in the documentation but not seeing much response out of the core. Not sure if this is a simulation issue or if all the communication will be handled behind the scenes.
Thanks