Forum Discussion
Occasional ContributorProgramming S25FL256 through Cyclone 10 with file from Processor
Hi,
signaltap waveform shows that you don't understand Avalon MM timing requirements. We see e.g. mem_read active while mem_ waitrequest is asserted which must never happen.
Imagine that mem_write starts a serial flash cycle with adress and data bits. Waitrequest indicates ongoing serial interface activity, next memory read/write can't happen before waitrequest is release. Similar problems exist with csr interface.
Super ContributorHi,
accessing flash connected to AS configuration pins doesn't require specific IP, just some assignments in Quartus. Also Quartus IP like altasmi_parallel, ASMI Parallel II and Generic Serial Flash Interface IP have the option to either use internal "hidden" connection to configuration pins or to export it manually. In the latter case it's the same situation as if you are using your own flash controller.
Dual-purpose pin settings in Device and Pin Options of all connected configuration pins must be "use as regular I/O"
