Programming of the CRAM of a Max10 using svf file

Dear Aiman

Thanks for your reply! There is no error message, but the issue is the following:

1.) We configure the FPGA CFM using a design, let's say "led_blinky"

2.) We power-cycle the FPGA; "led_blinky" is running (as it should)

3.) We use the .svf file (see above) to configure the CRAM of the FPGA with the design "stopwatch"

4.) We observe, that the design "stopwatch" is working as expected.

5.) Now comes the surprise: Although the design "stopwatch" was only supposed to be loaded into the CRAM (so it should not affect the design "led_blinky" in CFM), our previous design "led_blinky" is not running after power cycling the FPGA. Instead, neither of the two designs are active.

This problem is therefore not solved and unlikely related to the clock frequency.

Is there anything we can try in addition?

Thanks a lot!

Best,

Yves