problems with transmitter PLL input - Stratix II GX

The transmit PLL reference clock cannot be driven from anything but a PIN on the FPGA. It cannot be driven from a PLL. This is done intentionally to reduce jitter on the transmit pll reference clock although I'm sure the guys at Altera know how to shut this restriction off. Xilinx used to implement the same restriction but they've removed it with Virtex V due to better jitter than they previously thought.

One thing you might be able to do (depending on your board) is route a PLL output out of the chip and back into another PLL input pin. Then you could drive you 80MHz clock out and use the feedback input to drive the transmit PLL and Quartus won't know you're breaking the rules. You're jitter performance would likely not be very good.

Yes you're supposed to have a reference clock between 50MHz and 622.08 MHz. You could try and trick the transceiver by configuring everything to be twice the data rate of what you really need and tell it you're giving it an 80MHz reference clock but then just feed it with a 40MHz clock. I don't recommend this and I have no idea what the result would be. You would be running the transceiver's clock multiplier at it's maximum setting. I really don't recommend this.

Jake

Hi Jake,

and thanks for the answer. Now everything is a little bit clearer. Bye!

Hi everybody,

I have a doubt on the receiver section of the stratix II gx , related to the previous posts in this thread. The situation is the same of my first post, ok I've understood there's no possibility to have the tx section working with my setup, fine.

The doubt is about the rx section: when I had the problem with the tx, I've opened a service request about it on altera website ("mysupport").

I had some mail exchange with them, but I still don't understand their final answer to my requests. We were talking about the possibility of obtaining a 1600 Mb/s datarate with my current setup (only 40 Mhz clk on my custom board). Here is his answer:

" It is impossible to obtain a rx datarate of 1600 Mb/s or of 800 Mb/s, clocking the ALT2GXB receiver with a 80 Mhz clock, which is the output of another PLL. The reason is that the clock of ALT2GXB must come from pin and does not support the output of another PLL. "

BUT I have some code developed by a colleague, for the same board, working fine with a 800 Mb/s datarate. The code was implemented in a "real" situation (no just simulation) , and it fully worked.

So, should I trust my colleague or Altera support? :confused:

thanks to anybody who can help me to clarify this matter, all the best,

C

yes of course I have code from my colleague: full compilation returns no error, even if I try to change the ALT2GXB settings to obtain a datarate double of his (1600 vs 800 Mb/s)

My question was about understanding as much as possible the ALT2GXB settings and behaviour, not just who to trust. So the correct question should be the same I sent to support:

"It is possible to obtain a rx datarate of 1600 Mb/s with a Stratix II GX, having available on board only a 40 Mhz clock? (and so feeding the RX section with a 80 Mhz clock, output of a FPGA PLL?)"

Well let's backtrack a little bit. Your initial issues were concerning the TX side and how to obtain an 800Mbps data rate when all you had available was a 40MHz clock. I assume you've resolved this issue.

Now let's clarify a few things. Is the code that your colleague gave you feeding the ALT2GXB instance with a clock driven from a PLL within the FPGA? If it is then yes the answer that Altera support gave you, and the answer I gave you and the Stratix II GX user's guide are all wrong.

As far as Altera support goes. My experience is that it's always best to contact your FAE rather than put in a support request when you have technical questions like this.

Now with regards to RX. When the datarate of the received signal is greater than 622Mbps, the Clock Recovery Unit of the transceiver can automatically detect and recover the clock frequency given that certain other conditions are met (see volume 2 of the Stratix II GX Handbook). It's highly possible that you could feed the Receiver with a 40MHz reference clock and it would still be able to recover the 800Mbps clock from the incoming data stream.

Would you be able to post your Verilog file containing your ALT2GXB megafunction?

Hi Jake, and thanks for your answer. You are right, let's try to summarize my situation:

Setup: Stratix II GX in a custom board, only 1 clock available (FPGA LVDS input, pin AN19) - 40 Mhz. The datarate of my application is 1600 Mb/s, always.

The code from my colleague (as wrote, fully working in a real environment) was using the same board, but with a 800 Mb/s RX datarate. And yes, he is feeding the ALT2GXB instance with a 80 Mhz clock driven from a PLL within the FPGA. But ONLY for RX side, no TX at all.

My initial issue (start of this thread) was about the TX side because I was trying to implement the BIST (PRBS). I had 1 error from the compiler, regarding the TX PLL, this one:

s2gx:U2|alt2gxb:alt2gxb_component|channel_quad.pll0 is fed by PLL output

So I gave up, understanding that it was impossible to have my FPGA transmit with my current setup, owing also to the answers I got in this forum, from the manual and from the support. Anyway, let's consider this solved (at least understood)

Second step: this custom board is mainly dedicated to RX, so in the service request I've opened I asked if it was possible to obtain my desidered datarate (1600, not 800) in RX (given that was no possible in TX). The answer was the one I've posted in this thread on the 9th of May, and was negative for both datarates. But to be honest I didn't find anything in the manual explaining me this point (for the TX, I've found it)

Your answer (I think you are referring to you first answer in this thread) was ok, because it was referring to the TX side of the transmitter. I've already contacted my FAE - was my first support attempt before altera and this forum - , but he suggested me to open a service request on mysupport.com and/or to contact the board designer, who is my colleague who also wrote the code.

As you requested, I am posting here my file containing my ALT2GXB megafunction (alt2gxb_s.vhd) . It's VHDL, unfortunately I don't work with verilog. If you need my VHDL code instancing the megafunction, I can post also that one.

Thanks since now for your answers, all the best,

C.