Honored Contributor
Honored ContributorThe transmit PLL reference clock cannot be driven from anything but a PIN on the FPGA. It cannot be driven from a PLL. This is done intentionally to reduce jitter on the transmit pll reference clock although I'm sure the guys at Altera know how to shut this restriction off. Xilinx used to implement the same restriction but they've removed it with Virtex V due to better jitter than they previously thought.
One thing you might be able to do (depending on your board) is route a PLL output out of the chip and back into another PLL input pin. Then you could drive you 80MHz clock out and use the feedback input to drive the transmit PLL and Quartus won't know you're breaking the rules. You're jitter performance would likely not be very good. Yes you're supposed to have a reference clock between 50MHz and 622.08 MHz. You could try and trick the transceiver by configuring everything to be twice the data rate of what you really need and tell it you're giving it an 80MHz reference clock but then just feed it with a 40MHz clock. I don't recommend this and I have no idea what the result would be. You would be running the transceiver's clock multiplier at it's maximum setting. I really don't recommend this. Jake
