problems with transmitter PLL input - Stratix II GX

yes of course I have code from my colleague: full compilation returns no error, even if I try to change the ALT2GXB settings to obtain a datarate double of his (1600 vs 800 Mb/s)

My question was about understanding as much as possible the ALT2GXB settings and behaviour, not just who to trust. So the correct question should be the same I sent to support:

"It is possible to obtain a rx datarate of 1600 Mb/s with a Stratix II GX, having available on board only a 40 Mhz clock? (and so feeding the RX section with a 80 Mhz clock, output of a FPGA PLL?)"