problems with transmitter PLL input - Stratix II GX

Well let's backtrack a little bit. Your initial issues were concerning the TX side and how to obtain an 800Mbps data rate when all you had available was a 40MHz clock. I assume you've resolved this issue.

Now let's clarify a few things. Is the code that your colleague gave you feeding the ALT2GXB instance with a clock driven from a PLL within the FPGA? If it is then yes the answer that Altera support gave you, and the answer I gave you and the Stratix II GX user's guide are all wrong.

As far as Altera support goes. My experience is that it's always best to contact your FAE rather than put in a support request when you have technical questions like this.

Now with regards to RX. When the datarate of the received signal is greater than 622Mbps, the Clock Recovery Unit of the transceiver can automatically detect and recover the clock frequency given that certain other conditions are met (see volume 2 of the Stratix II GX Handbook). It's highly possible that you could feed the Receiver with a 40MHz reference clock and it would still be able to recover the 800Mbps clock from the incoming data stream.

Would you be able to post your Verilog file containing your ALT2GXB megafunction?