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Altera_Forum's avatar
Altera_Forum
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15 years ago

Problems with FLEX10KE

Hi all,

I have same firmware that burned on many boards. on 40% of the boards it runs without any problems. on other 60% it gives wrong results. I know for sure that the problem is in the FPGA itself (or in the firmware). I need help in order to solve it. where can be the problem? what can act in this strage way? how can I know for sure if it is a timing problems or functional, how can I find the problem and solve it?

Thanks ahead

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    What is the clock rate of the design? Do the designs all meet timing?

    Will the design function at a lower clock rate? Try reducing the clock rate on the bad boards and see if the problem clears. If it does, then its probably timing related.

    Have the boards worked in the past, and they are now failing, or have they never worked?

    What is the design? Does it depend on external interface logic? I have FLEX10KE boards that could be used for a comparison test.

    http://www.ovro.caltech.edu/~dwh/correlator/cobra_pics/cobra_corl.jpg (http://www.ovro.caltech.edu/%7edwh/correlator/cobra_pics/cobra_corl.jpg)

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Acording to Quartus this design can work with up to 16MHz, the crystal is 8MHz no PPL used.

    Part of the design is communication with other boards, I cannot reduce clock freq so easyly.

    To day there are boards that works perfect (40%), but also threre are many boards that doesn't work (60%).

    The design mesures errors in step motor position and speed.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    --- Quote Start ---

    Acording to Quartus this design can work with up to 16MHz, the crystal is 8MHz no PLL used.

    --- Quote End ---

    Did you specify a timing constraint of 8MHz, and the tool result was 16MHz, or was this just 'what you got'?

    16MHz is pretty low. What speed grade are the FPGAs? I use FLEX10KA devices (older generation) and they work fine at 33MHz. It could be that your design style is the source of your problem.

    --- Quote Start ---

    Part of the design is communication with other boards, I cannot reduce clock freq so easily.

    --- Quote End ---

    No problem, it was just a debugging suggestion.

    --- Quote Start ---

    The design measures errors in step motor position and speed.

    --- Quote End ---

    I recently had to 'fix' a design that was a motor control interface. The original designers did not adequately decouple the FPGA, and there was lots of signal glitching on sensor lines when motors started and stopped. I had to add 'glitch' filters on the sensors, where the filter only allowed a signal transition if the input signal changed state and stayed in that state for 16us. The filtered signal was then sent to the control FSM internal to the FPGA.

    What kinds of problem are you seeing on the boards that do not work?

    Cheers,

    Dave