Problems with design example Low Latency Ethernet 10G MAC Intel FPGAIP

HI,

I can't see the pic attachment in this forum. The only attachment available is the log file only.

1. May I know are you using Arria 10 or Stratix 10 FPGA for the sim run ?
2. Looking at your sim log file. The error is complaining it can't find certain design files in your Quartus project folder. Have you verified the design files is there in folder or missing ?
3. The other thing that I noticed is you are using Quartus v19.1 pro but pair with Modelsim 10.5b. Based on Quartus v19.1 Pro release note,you should be using Modelsim 106d instead to avoid sim tool compatibility issue.
4. Another possibility that I can think off is maybe either your Quartus project or Ethernet example design is corrupted.

My debug suggestion is :

• Create a new Quartus project and generate new Ethernet example design
• Then run sim again using Modelsim 10.6d as your example design is generated from Quartus pro v19.1

Thanks.

Regards,

dlim

Hello, I will try to attach again the picture,

on the other hand I tried your solutions, I've created a new project example and ran it with the 10.6d with same results,

HI,

Thanks. I can see your attachment image now.

• Can you confirm are you using Cyclone 10 GX FPGA or which FPGA ?
• Also, can you share screen shot of the Ethernet "IP" page instead of "example design" page. It's good to know what setting that you configured

So, Modelsim 10.6d still failed ya.

• Have you looked into the sim log error message to locate the design files to see they are really missing in project folder or so ?
• Btw, I also found below known issue in the past. You can try shorten your Win Quartus project folder path and see
  • https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/hsio/2019/error---vlog-7--failed-to-open-design-unit-file-------------rtl-.html

Thanks.

Regards,

dlim

Yes, I'm using 10GX220YF780 .

I changed the path to a shorter one and it seems to work!, but now the simulation stops in a different point. See log attached

I attached the IP configurations aswell

HI,

It's good to know that sim can compile the design successfully now after shorten the design folder path but looks like you bump into new sim halted issue.

I dig into KDB link again and found out below link. I highly encourage you to checkout the KDB link from time to time as well to find out some clue that maybe able to help resolve your issue.

• https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/ip/2020/why-does-the-low-latency-ethernet-10g-mac-intel--fpga-ip-generat.html

Looks like there could be some issue with sim design generated from older Quartus version.

Kindly use latest Quartus v19.4 to regenerate new sim project again and give it another try.

Thanks.

Regards,

dlim

With Quartus v19.4 I have the same results as before, attached file

Thanks for feedback.

Let me test out the v19.4 example design from my side as well.

Regards,

dlim

Hi,

I just gotten feedback from Intel Engineering team.

Sim run with Modelsim Intel FPGA may take 8 to 12 hours to complete.

• May I know how long did you run the sim ? Else I suggest you to rerun the sim again
• I will also try run the sim from my side overnight to check the result

If you need faster sim run time, then the better option will be to use Modelsim SE version instead.

Thanks.

Regards,

dlim