Forum Discussion
eamun1
New Contributor
New ContributorProblems with design example Low Latency Ethernet 10G MAC Intel FPGAIP
I've created the Design example base on the Low Latency Ethernet 10G MAC Intel FPGAIP, with the following parameters I open the project and suscessfully compile it, I try to run the simulation a...
Deshi_Intel
Regular Contributor
Regular ContributorHI,
It's good to know that sim can compile the design successfully now after shorten the design folder path but looks like you bump into new sim halted issue.
I dig into KDB link again and found out below link. I highly encourage you to checkout the KDB link from time to time as well to find out some clue that maybe able to help resolve your issue.
- https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/ip/2020/why-does-the-low-latency-ethernet-10g-mac-intel--fpga-ip-generat.html
Looks like there could be some issue with sim design generated from older Quartus version.
Kindly use latest Quartus v19.4 to regenerate new sim project again and give it another try.
Thanks.
Regards,
dlim
