Problems with design example Low Latency Ethernet 10G MAC Intel FPGAIP

HI,

Thanks. I can see your attachment image now.

• Can you confirm are you using Cyclone 10 GX FPGA or which FPGA ?
• Also, can you share screen shot of the Ethernet "IP" page instead of "example design" page. It's good to know what setting that you configured

So, Modelsim 10.6d still failed ya.

• Have you looked into the sim log error message to locate the design files to see they are really missing in project folder or so ?
• Btw, I also found below known issue in the past. You can try shorten your Win Quartus project folder path and see
  • https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/hsio/2019/error---vlog-7--failed-to-open-design-unit-file-------------rtl-.html

Thanks.

Regards,

dlim