Problem with Target connection

Hello,

I postet a request in another thread, but it fits here as well:

http://alteraforums.net/forum/showthread.php?t=24758

the system works well with one custom sopc module added to the system, but with an other one the system id and time stamp cannot be read from the board (de2-115 or de3 => it's not caused by the board but by the software/hdl-design).

the custom sopc module of course compiles correctly. but it is very large in size (2.500 lines of verilog code).

is there maybe a practical limitation of logic size due to delay times? (i don't really belief that...)

and why does the nios processor not respond anymore, even if the module isn't working correctly?

=> how can a faulty memory mapped slave module affect the processor? the mm-interface itself cannot be wrong because it is simulated, recognised correctly by the sopc builder and used by me in some other working designs "copy-and-paste".

in the meantime I checked the mm slave interface of the module with the signal tap analyzer and put a counting signal on the read-bus data output: this works.

The module also has a streaming interface: there is nothing on the bus => OK

but when I try to read the system ID: the system is reset (counter = 0) and the system ID is not found :cry:

Hi Mumble,

I don't know. This simply sometimes happens when you start adding, removing, changing, etc. In all dev tools, not only Altera.

If you kept the old project and you want to discover more (possibly to avoid the same mistake in the future...) you can compare the project files and try to find out what's the critical difference.

Cris

Hi Cris,

Thanks alot for your help.

I tried to build whole project from the scratch and this time it worked without a single error :) . I don't know the reason for those errors, as I did exactly the same thing as before.

Thanks,

Mumble.

Hi Mumble,

Signal check:

I presume you can easily do it with the SignalTap feature. Anyway I'm quite new to Altera, too and I never used it because I worked more on software side; so I can't give you better hints than looking at the signaltap manual or some tutorial.

For what I've done so far on the hw side, it was enough the raw old method: connecting signals to be tested to some fpga spare pins and recompiling; you can do this if your design recompiles fast.

System id:

Have you any failing timing in Quartus?

If not, it could be that something of the previous configuration is still around. Have you rebuilt everything?

As a last option I'd suggest to create a new project from scratch, with the same source files.

Regards

Cris

I am new to altera and don't know how to check it. kindly suggest.

Now I am getting different error:

Actual system ID not found on target at base address.

Even after removing the custom component.

Mumble

Hi Mumble,

jtag default settings are fine.

Then you were right, the problem is with your custom component.

What type of connection does it have in sopc builder?

Does it have an avalon master port or anything else which could block Nios operation?

Cris

I tried to rebuild the whole design. Now it is showing following error:

Actual system ID not found on target at base address.

Mumble

Yes, the design is working without custom component. I tried to run different designs too and they are working fine.

Do I need to add some specific setting for jtag when I am adding my owm component.

I have kept the default settings for JTAG.