Problem with Target connection

Hello,

I postet a request in another thread, but it fits here as well:

http://alteraforums.net/forum/showthread.php?t=24758

the system works well with one custom sopc module added to the system, but with an other one the system id and time stamp cannot be read from the board (de2-115 or de3 => it's not caused by the board but by the software/hdl-design).

the custom sopc module of course compiles correctly. but it is very large in size (2.500 lines of verilog code).

is there maybe a practical limitation of logic size due to delay times? (i don't really belief that...)

and why does the nios processor not respond anymore, even if the module isn't working correctly?

=> how can a faulty memory mapped slave module affect the processor? the mm-interface itself cannot be wrong because it is simulated, recognised correctly by the sopc builder and used by me in some other working designs "copy-and-paste".

in the meantime I checked the mm slave interface of the module with the signal tap analyzer and put a counting signal on the read-bus data output: this works.

The module also has a streaming interface: there is nothing on the bus => OK

but when I try to read the system ID: the system is reset (counter = 0) and the system ID is not found :cry: