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Altera_Forum's avatar
Altera_Forum
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14 years ago

Problem? with RAM component. VHDL

I'm using a Megawizard-generated RAM. It doesn't have its data output registered, but still it takes a clock cycle to put correct datum on its output port. Is it maybe registered? I think i already worked with a RAM that inmediately changes it output state... i'm doing a MIPS-inspired processor as an exercise, so i need the whole circuit to work in one single clock cycle. I compilling for device of DE2... it's an old cyclone II

Thank a lot

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    In the embedded memory blocks you will have at least registers on the input side (address) so you will always need at least one clock cycle to get the data.

    Either design your CPU to compensate for the clock cycle, or try to implement the memory as registers instead. If the memory isn't too big it should fit.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I had and old package with a memory implemented using registers. Things work nicely now. Thanks a lot for your help.

    Source code is provided if someone who need something like this needs it.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    This code produces no registers.... just a massive array of latches (BAD)

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    oh yes, i realized it just after sending it, the one i'm using has a clk'event condition. Thanks for the comment.