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Altera_Forum's avatar
Altera_Forum
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14 years ago

Problem? with RAM component. VHDL

I'm using a Megawizard-generated RAM. It doesn't have its data output registered, but still it takes a clock cycle to put correct datum on its output port. Is it maybe registered? I think i already w...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

In the embedded memory blocks you will have at least registers on the input side (address) so you will always need at least one clock cycle to get the data.

Either design your CPU to compensate for the clock cycle, or try to implement the memory as registers instead. If the memory isn't too big it should fit.