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Altera_Forum
Honored Contributor
Honored ContributorProblem? with RAM component. VHDL
I'm using a Megawizard-generated RAM. It doesn't have its data output registered, but still it takes a clock cycle to put correct datum on its output port. Is it maybe registered? I think i already w...
Altera_ForumHonored Contributor
Honored Contributoroh yes, i realized it just after sending it, the one i'm using has a clk'event condition. Thanks for the comment.
