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Altera_Forum's avatar
Altera_Forum
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16 years ago

Problem with Modelsim List

Hello,

I am trying to use a simulate.do file to simulate a project in VHDL, add signals to a list and print this list to an external file. But, even though I am running the simulation until 1ms, in my list all signals go only until 660ns...

Here is a part of my simulate.do file:

vsim work.topNoC

set StdArithNoWarnings 1

add list sim:/topnoc/noc/router0000/sc/free

add list sim:/topnoc/noc/router0000/sc/mux_in

add list sim:/topnoc/noc/router0000/sc/mux_out

add list sim:/topnoc/noc/router0000/sc/sel

add list sim:/topnoc/noc/router0001/sc/free

... (more add list commands)

add list sim:/topnoc/noc/router0101/op_local/tx

run 1ms

write list list.lst

quit -sim

quit -f

I have also tried the log command instead of add list, but the result was the same.

Does someone have a solution for that?

Thanks in advance!

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    Hello,

    But, even though I am running the simulation until 1ms, in my list all signals go only until 660ns...

    --- Quote End ---

    What version of ModelSim are you using here? Try checking simulation options in Simulate Menu->Runtime Options. Here one can set limits on wlf file limit, simulation time limit and iteration limit. Do you have those things correctly in place?
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Thanks for the reply vizziee!

    I am using ModelSim SE 6.1f.

    I checked the runtime options and they are all ok (no size and time limits). Now I noticed that when I run this script in the command line of the ModelSim GUI, the log function works (it stores all the waves until 1ms), though the add list doesn't (it stores only the 4 first deltas of 0 ns).

    However, when I run the script using a bat file, neither the log nor the add list work...
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I've just tried with VCD files and the problem continues...

    All that modelsim stores are the values of all signals in the first timestamp (#0) and then stops!

    Does someone have an ideia? I really need to work around this problem....

    Thanks a lot!
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    a work around would be editing your VHDL test bench to save the data to file rather than ModelSim itself. look up vhdl textio.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Hi all!

    I ended up discovering the problem.... it was a very stupid mistake of my own... I wasn't simulating the code correctly.... sorry all for this...

    and tks vizziee and thepancake for the help!

    But now I have another question...

    Is there any way to add complex signals (like memories and not only bit or std_logic vectors) to a vcd file?

    tks again!