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Altera_Forum
Honored Contributor
Honored ContributorProblem with Modelsim List
Hello, I am trying to use a simulate.do file to simulate a project in VHDL, add signals to a list and print this list to an external file. But, even though I am running the simulation until 1ms...
Altera_ForumHonored Contributor
Honored Contributora work around would be editing your VHDL test bench to save the data to file rather than ModelSim itself. look up vhdl textio.
