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Altera_Forum's avatar
Altera_Forum
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16 years ago

Problem with Modelsim List

Hello, I am trying to use a simulate.do file to simulate a project in VHDL, add signals to a list and print this list to an external file. But, even though I am running the simulation until 1ms...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hi all!

I ended up discovering the problem.... it was a very stupid mistake of my own... I wasn't simulating the code correctly.... sorry all for this...

and tks vizziee and thepancake for the help!

But now I have another question...

Is there any way to add complex signals (like memories and not only bit or std_logic vectors) to a vcd file?

tks again!