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Altera_Forum's avatar
Altera_Forum
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7 years ago

Problem with FIR II core

Hello,

I am trying to use 11 taps symmetrical FIR using the IP Catalog in Quartus 14.1

My data are in signed Q.15 format with sampling rate 288MHz.

I get the data in packets of 4 samples (64bits) on each 72MHz tick

and I want the filter to produce the data in packets of 4 samples quads (64bits)

I have setup the FIR II instance with the following parameters:

-single Rate,

-interpolation and decimation are 1

-one channel

-72MHz clock rate

-288MHz sample rate (so I use TDM and my input and output are 64bits)

-no back preasure

-Symmetrical filter ( 0.005798526799750 -0.000976593987326 0.010162681180614 -0.004699858564008 0.094485468273818 0.731713045004217

0.094485468273818 -0.004699858564008 0.010162681180614 -0.000976593987326 0.005798526799750)

Filter gain is 0.94125

- Coefficients Signed Fractional Binary, 15 fractional bits

- I have imported 11 floating point coefficients (it is strange that the frequency response is not shown,

the figure is scaled out of my curve and the impulse response is shown as 0 line. For now I assume it is a bug in the tool)

- Input option is signed fractional binary with 15 fractional bits and 16 bits in total.

- Output option is signed fractional binary, I truncate 15 LSB bits and 5 MSB bits so I get signed Q.15 as a result.

- The filter is clocked with 72MHz clock (the same clock I get my quads at)

- on the 'valid' input I set constant 1'b1

- On the 'error' signal I set constant 2'b00

I can pass both the input and the output of the filter to the DAC and can monitor the analog signal on the oscilloscope.

Also I can pass some data on the FPGA output pins to look at with the logic analyzer.

What I have checked so far:

1. If I pass constant data to the filter and it responds as I expect in the full Q.15 range at the input. (checked on logic analyzer)

2. I get 'valid' output as constant 1 and I get output 'error' as constant 2'b00

3. If I apply clean 10MHz full scale sine wave (I have verified it on the oscilloscope ) I get distorted signal

as it is shown on the screenshot.

I have tried to reduce the signal amplitude with the same distorted result.

I have reduced the filter coefficients resolution to speed up the filter and check

if this is speed performance issue but the result was even worse.

Anyone having an idea how to investigate further?

Thank you.

Dimitar

18 Replies

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  • Altera_Forum's avatar
    Altera_Forum
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    7 years ago

    --- Quote Start ---

    Thank you kaz!

    I'll try to derive 288MHz

    As a separate question.

    Do you think that there is simple solution of what i want with IP Catalog FIR II core in 72MHz domain?

    Thanks

    Dimitar

    --- Quote End ---

    The short answer is no

    you can use two parallel sections as even odd samples @ 144. You will need four sub-filters, not worth it and has to be done by hand not fir compiler. After all I assume your output may have to be one stream @ 288
  • Altera_Forum's avatar
    Altera_Forum
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    7 years ago

    I see.

    Actually my output should be passed the same way I get it (4 consecutive samples at once on each 72Mhz tick).

    My current system is using 72MHz clock.

    The odd/even structure you have in mind is something similar as the polyphase filter decomposition from the multi rate theory I guess?
  • Altera_Forum's avatar
    Altera_Forum
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    7 years ago

    OK Now I have 288MHz clock to my FIR filter but I seems to get issues with it.

    I have verified that filter 'valid' signal is constant 1 and filter output error[1:0] is 2'b00

    Is this a confirmation that the filter manages to do its calculations on time?

    What is to be expected if the clock reaches the filter maximum performance speed?

    Thanks

    Dimitar
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    7 years ago

    --- Quote Start ---

    OK Now I have 288MHz clock to my FIR filter but I seems to get issues with it.

    I have verified that filter 'valid' signal is constant 1 and filter output error[1:0] is 2'b00

    Is this a confirmation that the filter manages to do its calculations on time?

    What is to be expected if the clock reaches the filter maximum performance speed?

    Thanks

    Dimitar

    --- Quote End ---

    vin should be continuously high (by your input mux). vout will then be continuously high(by filter). It is single rate so both input and output are running on 288Mhz which is your data rate.

    Your question on filter maximum speed implies some uncertainty of your thoughts here. can you explain it further.
  • Altera_Forum's avatar
    Altera_Forum
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    7 years ago

    OK sorry I was not clear.

    My filter contains 11 coefficients. It is symmetrical FIR.

    I am not sure how this is internally implemented but I guess I have 6 multipliers (because of the symmetry) and some adders.

    I guess multipliers are implemented by a dedicated blocks and probably they all work in parallel?

    Anyways I was wondering what will happen if the period of my clock is shorter compared to the time needed for internal FIR logic to complete the calculations of the current output sample. Will the filter clear the output 'valid' flag in this case?

    I have no idea if with my 288MHz and 11 taps I am close to this point or not? I am using Stratix IV.

    Clarification is very welcome.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    7 years ago

    --- Quote Start ---

    OK sorry I was not clear.

    My filter contains 11 coefficients. It is symmetrical FIR.

    I am not sure how this is internally implemented but I guess I have 6 multipliers (because of the symmetry) and some adders.

    I guess multipliers are implemented by a dedicated blocks and probably they all work in parallel?

    Anyways I was wondering what will happen if the period of my clock is shorter compared to the time needed for internal FIR logic to complete the calculations of the current output sample. Will the filter clear the output 'valid' flag in this case?

    I have no idea if with my 288MHz and 11 taps I am close to this point or not? I am using Stratix IV.

    Clarification is very welcome.

    --- Quote End ---

    FPGA -unlike software- can work from full parallism to full serial processing as chosen by designer.

    It may require pipeline delay for timing closure issues i.e. output could be late but then it is fixed initial delay and stream comes out continuous thereafter.
  • Altera_Forum's avatar
    Altera_Forum
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    7 years ago

    If I have to ask different way.

    What do you think is the maximum clock rate I can clock my 11 taps symmetric FIR from the IP core

    if enough resources on Stratix IV silicon?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    7 years ago

    --- Quote Start ---

    If I have to ask different way.

    What do you think is the maximum clock rate I can clock my 11 taps symmetric FIR from the IP core

    if enough resources on Stratix IV silicon?

    --- Quote End ---

    In fpga jargon you are asking for "fmax". That is implementation issue. For a good design you can well get 300MHz in your device