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Altera_Forum's avatar
Altera_Forum
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8 years ago

Problem with FIR II core

Hello, I am trying to use 11 taps symmetrical FIR using the IP Catalog in Quartus 14.1 My data are in signed Q.15 format with sampling rate 288MHz. I get the data in packets of 4 samples (...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

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If I have to ask different way.

What do you think is the maximum clock rate I can clock my 11 taps symmetric FIR from the IP core

if enough resources on Stratix IV silicon?

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In fpga jargon you are asking for "fmax". That is implementation issue. For a good design you can well get 300MHz in your device