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OK sorry I was not clear.
My filter contains 11 coefficients. It is symmetrical FIR.
I am not sure how this is internally implemented but I guess I have 6 multipliers (because of the symmetry) and some adders.
I guess multipliers are implemented by a dedicated blocks and probably they all work in parallel?
Anyways I was wondering what will happen if the period of my clock is shorter compared to the time needed for internal FIR logic to complete the calculations of the current output sample. Will the filter clear the output 'valid' flag in this case?
I have no idea if with my 288MHz and 11 taps I am close to this point or not? I am using Stratix IV.
Clarification is very welcome.
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FPGA -unlike software- can work from full parallism to full serial processing as chosen by designer.
It may require pipeline delay for timing closure issues i.e. output could be late but then it is fixed initial delay and stream comes out continuous thereafter.
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