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Honored Contributor
Honored ContributorProblem with FIR II core
Hello, I am trying to use 11 taps symmetrical FIR using the IP Catalog in Quartus 14.1 My data are in signed Q.15 format with sampling rate 288MHz. I get the data in packets of 4 samples (...
Altera_ForumHonored Contributor
Honored ContributorOK sorry I was not clear.
My filter contains 11 coefficients. It is symmetrical FIR. I am not sure how this is internally implemented but I guess I have 6 multipliers (because of the symmetry) and some adders. I guess multipliers are implemented by a dedicated blocks and probably they all work in parallel? Anyways I was wondering what will happen if the period of my clock is shorter compared to the time needed for internal FIR logic to complete the calculations of the current output sample. Will the filter clear the output 'valid' flag in this case? I have no idea if with my 288MHz and 11 taps I am close to this point or not? I am using Stratix IV. Clarification is very welcome.
