Problem with configure Stratix III with AS using EPCS128

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Configuration goes sucsessfuly only when i try to poke a tester to DATA or DCLK pin, even if tester (multimeret) is off

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So, it can be made to work if you connect something to DCLK or DATA? Is that right? Doing this will change the shape of the signal you are probing. It sounds like this subtle difference is enough to make it work.

How close is your EPCS to your FPGA? Do you have a series resistor in line from the EPCS DATA out pin to the FPGA's DATA0? I note the Stratix III handbook doesn't suggest this resistor but some newer families (see the cyclone iv configuration handbook (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-iv/cyiv-51008.pdf)) do and you appear to have a signal integrity issue. By probing the nets you're adding a load and slowing the signal edges down a little. This seems to be enough to allow the FPGA to configure.

If you can add this series resistor in (25R) I would.

Cheers,

Alex

Thanks for replying, Alex.

EPSC is close enough to FPGA, about 1-2cm.

I've already tried to add series resistor to DATA line, still doesn't work

I caught signal on DATA pin when EPCS start to configure after i connect probe to line.

And another strange thing: it started configuration when i soldered long wire to DATA pin (with another end left not conected like aerial) and resistor 56 kOhm to GND. :)

It's sounding more and more like a signal integrity issue, although 1-2cm is nothing to worry about.

Your scope plot doesn't look particularly reassuring. However, with the probe in contact the device configures? Is that right? If so, then the actual signal quality is not that bad. Any chance you can connect to a more local ground connection? Ideally, a soldered ground connection near the probe point. That will improve the trace somewhat.

Is this board a one off? Do you have another to try?

How good do you're power rails look? Check them all but specifically, VCCPGM and VCCL. VCCBAT isn't floating, is it?

Cheers,

Alex

I found what was wrong.

Ewerything about my hardware was ok, exept one thing: EPCS was not original altera divice and when FPGA begin to load data, it asked divice ID first (i think so).

I found another guy had same problem, but with configure ARRIA II.

Solution is simple: when i create JIC file, there are two options "Disable EPCS ID check" and "Disable AS mode CONF_DONE error check". I turned them on and configuration passed correctly =)

But i still don't understand how could i change divice ID with wire or probe conneccted to line))

Thank you for taking part in solving this problem

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I found what was wrong.

Ewerything about my hardware was ok, exept one thing: EPCS was not original altera divice and when FPGA begin to load data, it asked divice ID first (i think so).

I found another guy had same problem, but with configure ARRIA II.

Solution is simple: when i create JIC file, there are two options "Disable EPCS ID check" and "Disable AS mode CONF_DONE error check". I turned them on and configuration passed correctly =)

But i still don't understand how could i change divice ID with wire or probe conneccted to line))

Thank you for taking part in solving this problem

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I do not think you are able to change the device ID wwith wire or probe. Each device should have their own unique ID :)