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Configuration goes sucsessfuly only when i try to poke a tester to DATA or DCLK pin, even if tester (multimeret) is off
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So, it can be made to work if you connect something to DCLK or DATA? Is that right? Doing this will change the shape of the signal you are probing. It sounds like this subtle difference is enough to make it work.
How close is your EPCS to your FPGA? Do you have a series resistor in line from the EPCS DATA out pin to the FPGA's DATA0? I note the Stratix III handbook doesn't suggest this resistor but some newer families (see the
cyclone iv configuration handbook (
https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-iv/cyiv-51008.pdf)) do and you appear to have a signal integrity issue. By probing the nets you're adding a load and slowing the signal edges down a little. This seems to be enough to allow the FPGA to configure.
If you can add this series resistor in (25R) I would.
Cheers,
Alex
Honored Contributor
