Problem with ALTCLKCTRL module and outputs from two different PLLs in Cyclone III

Hello!

I'v got a Cyclone III device EP3C16U256. And i have got a two external clock signals 10 MHz and 30 MHz (they are connected to dedicated clock pins on different sides of FPGA). I want to make 120 MHz clock from 10 MHz clock and 120 MHz clock from 30 MHz clock. And i want to dynamicaly switch between them (120 MHz from 10 MHz and 120 MHz from 30 MHz).

I wrote this code:

...
/*** PLL from 30 MHz to 120 MHz ***/    
omsp_pll omsp_pll_inst (
    .inclk0                     ( mclk ),
    .c0                        ( internal_ss_clk )
);
/*** PLL from 10 MHz to 120 MHz ***/
sync_pll    sync_pll_inst
(
    .inclk0                     ( sync_clk ),
    .c0                         ( sync_ss_clk ),
    .locked                     ( sync_pll_locked_sig )
);
/*** ALTCLKCTRL module ***/
clk_mux    clk_mux_inst
(
    .clkselect                 ( ss_clk_select_sig ),
    .inclk0x                 ( internal_ss_clk ),    
    .inclk1x                 ( sync_ss_clk ),    
    .outclk                 ( ss_clk_sig )
);
...

And i have an error in Quartus (Quartus II 64-Bit Version 13.1.0 ):

--- Quote Start ---

Error (15669): inclk port of Clock Control Block "clk_mux:clk_mux_inst|clk_mux_altclkctrl_uhi:clk_mux_altclkctrl_uhi_component|clkctrl1" must be driven by 1 PLLs but is driven by 2 PLLs

Info (15670): Clock Control Block is driven by PLL "omsp_pll: omsp_pll_inst|altpll:altpll_component|omsp_pll_altpll:auto_generated|pll1"

Info (15670): Clock Control Block is driven by PLL "sync_pll:sync_pll_inst|altpll:altpll_component|sync_pll_altpll:auto_generated|pll1"

--- Quote End ---

How can i solve this problem?