Problem with ALTCLKCTRL module and outputs from two different PLLs in Cyclone III

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Refer to Figure 5-1 'Clock Control Block' - page 5-5 - in chapter 5 of the 'cyclone iii device handbook (https://www.altera.com/literature/hb/cyc3/cyclone3_handbook.pdf)'.

Unfortunately, in Cyclone III at least, you're going to need an external loop, fed from one of your PLL outputs to a dedicated clock input pin associated with the Clock Control Block you're using. The Control Block is limited to using two (of the five available) clock outputs from a single PLL. There's no routing to allow a feed from a second PLL.

Cheers,

Alex

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Thank you very much for the detailed answer!