problem about clock control block
Hi,
When I use cyclone 10(10CL040YU484I7G)'s clock control block, I meet some problems.
In my application, there are 2 main clocks(one from clk pin and one from PLL), and 2 parts of main logic. I used 2 clock control blocks, and one for part A, the other for part B. But due to the inputs of 2 clock control blocks are same, Quartus says "Following nodes require the same Clock Control Block CLKCTRL_G10" in "place & route" phase.
Which logic will be chose which clock is only based on the clock chose logic. The clock chose logics of the two parts are independent. So I think I can't just use one clock control block.
I try to use LUT mux clock, but the quality of clocks are too bad to suit my application.What should I do? Why Quartus don't instence two Clock Control Block?
Thanks.