Forum Discussion
Justin569
New Contributor
New Contributorproblem about clock control block
Hi, When I use cyclone 10(10CL040YU484I7G)'s clock control block, I meet some problems. In my application, there are 2 main clocks(one from clk pin and one from PLL), and 2 parts of main logic. I u...
sstrell
Super Contributor
Super ContributorAre you saying that you've manually added the clock control block IP (twice) to the design? Try just coding the clock enable logic without the IP and see what happens. Quartus will (should) add clock control blocks automatically or whatever logic is required.
Justin569New Contributor
New ContributorHi sstrell, thanks for your attention. I directly used combinational logic for dynamical clock chosen before clock control block. But function didn't realised. Perhaps due to I hadn't constraint timming suitable. Nominally, the frequency of both master clocks is 125MHz. But the diffrence of frequency must exist. And they have diffrent phase. So I don't know how can I constraint the clock which chosen by combinational logic. Plase give me some guidance. Thank you.
