Forum Discussion
FvM
Super Contributor
3 months agoHi,
different FPGA families have calibration blocks with different properties. Cyclone 10 LP e.g. has separate Rup/Rdn and specifies that the applied voltage during calibration can be up to VCCIO (90 mW/100 ohm at highest VCCIO of 3V). But calibration completes in about 100 us, considering chip resistor time constant > 1 ms, there will be a huge power margin even for small 63 mW 0402. Cyclone V may apply lower maximal voltage to RZQ, but if not, I don't expect problems.
- Ian_Maw2 months ago
New Contributor
Thanks FvM.
I have used your answer for now but I will leave the question open for now.