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KJ's avatar
KJ
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14 days ago

Power and thermal characterization of Agilex 5

We are working on the power characterization of a design based on the Agilex5 E-series and I've come across a few questions I haven't been able to fully resolve from Altera's documentation. Would you...
Power
KJ's avatar
KJ
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12 days ago

Hi Farabi,

Thank you for your answers. They are very useful.

With regards to power consumption of uninstantiated DSP and M20K blocks, the report shows they also contribute to dynamic power consumption, as opposed to just leakage power. Could you clarify why?

With regards to powering down HPS/transceivers, choosing the part that doesn't have those in the first place would be ideal, but not all fabric sizes for Agilex 5 E come with that configuration option, unfortunately. 

Regards,

Chris

Farabi_Altera's avatar
Farabi_Altera
Icon for Regular Contributor rankRegular Contributor
8 days ago

Hello Chris, 

 

1- Power analyzer partitions device power into categories. Some infrastructure power may be allocated to DSP or RAM category even though no DSP arithmetic or memory read/write activity is occurring. 

2- Even individual blocks are power-gated, the surrounding clocking and infrastructure networks still exist on the die. The analyzer may distribute a portion of this activity into DSP/RAM categories. 

3- Power Analyzer includes small baseline dynamic values to account for device-level activity that cannot be cleanly assigned elsewhere. In nearly empty design, these baseline values can appear in the calcualtion. 

 

regards,
Farabi