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Altera_Forum
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16 years ago

Porting from Xilinx to Altera

Hi everybody,

we just started with a new project which will use an Cyclone III. We ant to reuse as much of our previous code which was done for Xilinx FPGA.

Most file are quite genric, but some contain components from xilinx library.

We would replace this part with using if generate constructs, depending on FPGA types, but there is still the unisim library declaration at the top of the file.

As anybody had any expirience with that ? i thought about making a dummy unisim library which conatins the used components, to be able to actually compile the code. Is that the right approach ?

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