Porting from Xilinx to Altera

Hi Rysc

Thanks for your response. I found the user guides section on the web, which is what I was looking for - has info on mem, pll etc so possibly my documentation needs have been forfilled.

I created a PLL through the megawizard and was happy to find that the resulting VHD file was referencing the altera_mf in the same way that I did it manually. The problem that I currently face in using the megawizard is that I have to use it each time I want to ie: create a PLL with a different mult/div ratio, as I cant bring those generics out of the wrapper entity. I would rather have one PLL file that has some flexiblilty rather than multiple 'dedicated' PLL's. I think I really only need to convert the DCM's and the BRAMs across as the rest is just VHDL. I'll probably use the megawizard output as a reference and then make my custom file, bringing out the generics that I want to keep flexible, plus maybe add a few comments to attempt to keep the confusion to a minimum :)