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Altera_Forum
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14 years ago

PLLs could be used to reduce the influence of noise ?

Hi,

I remembered that i read from somewhere that 2 PLLs can be used to reduce the influence of noise during data transfer? or during FIFO rate matching? when having 2 external clock source.

For example, the incoming data stream comes from an ADC at 60MHz, and an outgoing stream going to a laptop at 48MHz through a DCFIFO, but before these external clock of 60MHz, and 48MHz goes into a FIFO, it is used as an input for 2 PLLs producing the same clock speed respectively.

I don't see the reason of using 2 PLLs for producing the same clock speed.. but it is said to have the effect of reducing the influence of noise from the environment... is it true?? or is it for some other reason?

Thank you.:)

Regards,

Michael

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    If your clock has noise on it, a PLL can filter it out. Remember that it's basically an oscillator that is being tuned to match its edges(through a feedback path) with your incoming edges. So if there is noise on your clock tree and there is no PLL, it might create a spurious edge in the device which could be disastrous, while a PLL might see that edge and make a slow modification to try and track it(depending on bandwidth settings) but it would basically filter it out. I have seen designs where that worked(although we still suggested going back and cleaning up the external clock).

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Interesting....

    So using PLLs are common practice in filtering out surrounding noises?

    otherwise, what are other option of doing so?

    Thank you for your reply.

    Regards,

    Michael
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    All designs I see use PLLs, and for the most part that is not why they are selected(just a nice benefit). The two big things are:

    - Creating different clocks(whether it be faster, slower, phase-shifts, etc.)

    - Better I/O timing

    The basic premise is that a clock tree should not have noise. I believe it gets routed first with highest priority, and wouldn't be surprised if there are board design rules to isolate it(although I'm really moving out of my expertise and could be wrong). I do see users simulating their clock connections with board sim tools like hspice, as well as measuring it on real hardware to make sure it correlates. A noisy clock is pretty much fatal to a design.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I won't expect a FPGA PLL to remove spurious edges from the INCLK. It utilizes a digital phase detector, that needs to "count" edges. I would rather fear immediate unlock as result of a single spurious edge.

    A slow PLL can reduce phase jitter to a certain extent. But the Altera suggestions for PLL usage don't give the impression, that the FPGA PLLs are particularly suited for this job. They e.g. say, when cascading PLLs, the second one should always have fast filter settings.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Although I have seen it work at removing noise, I wouldn't rely on it for that, i.e. the system shouldn't have clock noise to begin with. And if it loses lock(and allowing the system to see the problem) that is a lot better than a double-edge inside the fabric.