PLLs could be used to reduce the influence of noise ?

I won't expect a FPGA PLL to remove spurious edges from the INCLK. It utilizes a digital phase detector, that needs to "count" edges. I would rather fear immediate unlock as result of a single spurious edge.

A slow PLL can reduce phase jitter to a certain extent. But the Altera suggestions for PLL usage don't give the impression, that the FPGA PLLs are particularly suited for this job. They e.g. say, when cascading PLLs, the second one should always have fast filter settings.