Honored Contributor
Honored ContributorAll designs I see use PLLs, and for the most part that is not why they are selected(just a nice benefit). The two big things are:
- Creating different clocks(whether it be faster, slower, phase-shifts, etc.) - Better I/O timing The basic premise is that a clock tree should not have noise. I believe it gets routed first with highest priority, and wouldn't be surprised if there are board design rules to isolate it(although I'm really moving out of my expertise and could be wrong). I do see users simulating their clock connections with board sim tools like hspice, as well as measuring it on real hardware to make sure it correlates. A noisy clock is pretty much fatal to a design.
