Honored ContributorHello all,
I've noticed that many use PLL on the reference clock input even if they do not need to divide/multiply/shift this clock or do not have external clock to synchronize to the reference frequency. For example 50 MHz input clk goes to PLL and then 50MHz c0 is used everythere in the design. What is the purpose of this type of PLL usage? Thank you in advance.
Honored ContributorThe PLL can be used to clean up (de-jitter) the input clock before using it in the system.
JakeHonored ContributorInteresting. I thought PLLs are sensitive to jitter.
Means that typical PLL is only as good as the reference clock that is supplied to it, because the phase detector seeks to continually adjust the VCO to match the incoming reference. Maybe loop filter with a long time constant can be used to reduce jitter.... And what will be if the PLL has a noisy analog power supply? ThanksHonored ContributorEverything you mentioned is true. Altera PLLs have various bandwidth settings. The "PLL usage" report in the Quartus fitter results will tell you specifically what the resulting bandwidth of your PLL is. The PLLs internal to the FPGA will help remove high-frequency jitter.
Also, jitter on the input clock will be integrated through the PLL. (So square wave jitter looks like a sawtooth, sawtooth looks like a parabolic, etc.) The integration of random jitter is theoretically 0. It can be a lot of fun to inject jitter onto the input clock and measure the jitter on the PLL output clock. The PLLs can also clean up the duty cycle on a clock. You are also correct that noise on the PLL analog supply can translate to jitter on the clock outputs. It can also be a lot of fun to inject noise on the analog supply and watch the resulting jitter on the output clock. JakeHonored ContributorHi,
You could also use the PLL to "free-run" if you suddenly loose the input clock. This might allow your design enough time to enter a safe state. A sudden loss of the clock might leave your design in an unsafe state if it is not accompanied by an asynchronous reset. Regards, NikiHonored ContributorCool.
Jake, what type of PLL (options in the altpll megawizard) should I specify to guarantee that my PLL will remove a jitter? Niki, if the registers in my design all have an asynchronous reset, should i still use a PLL to enter a safe state? Thak you for your help.Honored ContributorI'm new member, just test my account!
Honored ContributorGuarantee huh ... no guarantees. The effectiveness of the PLL at removing jitter depends entirely on the type of jitter in the signal. Obviously the simple answer is to set the bandwidth of the PLL as low as possible.
Your original question was why designs use a PLL to produce a clock of the same frequency as the input clock. The simple answer is that a PLL can clean up the clock (jitter, duty cycle, etc.). Some clock outputs from crystal oscillators can look kind of trashy. Doesn't hurt to run it through a PLL. JakeHonored ContributorJake, all is clear.
Thank you very much.Honored Contributorthe PLL helps balance setup and hold timing to meet i/o constraints which explains using it with a 1:1 ratio:
http://www.altera.com/literature/wp/wp_stxtco.pdfHonored ContributorAs a follow up to this discussion on the PLL being possibly used to clean up input clock jitter, does anyone know if Timequest takes this into account when reporting the resulting clock uncertainty?
I've tried applying the set_clock_uncertainty command to the PLL input clock but when I look at the timequest report, this uncertainty appears to be directly transferred to the latch clock (PLL output) uncertainty in the data required path of a setup/hold analysis. This was somewhat unexpected, but I'm wondering if anyone else has experience with this. Raphael
