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Altera_Forum
Honored Contributor
Honored ContributorPLL usage
Hello all, I've noticed that many use PLL on the reference clock input even if they do not need to divide/multiply/shift this clock or do not have external clock to synchronize to the reference fr...
Altera_ForumHonored Contributor
Honored ContributorEverything you mentioned is true. Altera PLLs have various bandwidth settings. The "PLL usage" report in the Quartus fitter results will tell you specifically what the resulting bandwidth of your PLL is. The PLLs internal to the FPGA will help remove high-frequency jitter.
Also, jitter on the input clock will be integrated through the PLL. (So square wave jitter looks like a sawtooth, sawtooth looks like a parabolic, etc.) The integration of random jitter is theoretically 0. It can be a lot of fun to inject jitter onto the input clock and measure the jitter on the PLL output clock. The PLLs can also clean up the duty cycle on a clock. You are also correct that noise on the PLL analog supply can translate to jitter on the clock outputs. It can also be a lot of fun to inject noise on the analog supply and watch the resulting jitter on the output clock. Jake
