As a follow up to this discussion on the PLL being possibly used to clean up input clock jitter, does anyone know if Timequest takes this into account when reporting the resulting clock uncertainty?
I've tried applying the set_clock_uncertainty command to the PLL input clock but when I look at the timequest report, this uncertainty appears to be directly transferred to the latch clock (PLL output) uncertainty in the data required path of a setup/hold analysis. This was somewhat unexpected, but I'm wondering if anyone else has experience with this.
Raphael