PLL Reconfiguration problem on Cyclone3

The best way (in my opinion) to dynamically reconfigure a pll is to use the "altpll_reconf" megafunction.

I feed my pll with a 24MHz clock and the "reconf" block with a 6MHz clock. I also use ROMs ("altsyncram") to store the data to reconfigure the pll. The "altpll_reconf" create "pll_scanclk" which is used to feed the ROMs. Pulse, one pll_scanclk cycle, on "write_from_rom", wait enough time, then pulse on reconfig, one pll_scanclk cycle again.

It works for me with clk from external signals or from another pll.

Second thing, make sure your design is clean. When you copy a folder with a design inside, quartus do a lot of bad links. So make sure that all your .vhd are well linked, that there are no problem with the "inst&&&" etc... This could make several strange effects. for example, one of my design mixed the output of my pll after reconfig, and make a cleaned project solved the problem.

good luck!

I'm not quite following your question. What clock were you using as the reconfig clock before? You certainly can't use one of the pll's outputs as the reconfig clock.

Also remember that the maximum scanclk frequency is 100MHz and I expect that's a best case scenario and may be lower for slower speed grades.

Typically I've provided a 50MHz clock from a seperate PLL as the reconfiguration clock.

Jake

Setup:

• PLL generated from MageWizard with thre clockes

• PLL Reconfig Megafunction

• 2 ROM generated from Megawizard

• State machine to start the PLL Reconfig Megafunction, based on the example in the user guide

• FPGA: Cyclone3, 40 (120 on eval board), 780 pins packet, speed grade 8 (slowest)

All VHDL files are linked correctly. To run the configuration I use a 72 MHz clock egnerated from 125 MHz clock in a PLL. In this case the PLL stop working.

Then I made a design with the eval board, just to get the PLL reconfig work. In this case I only made it work when I used the clock from 50 MHZ onboard oszilator. If I used a clock from a PLL or a external clock with another frequency it doesn't work.

@mazel: Waat do you defines as "waiting enough time" between the ROM reading and the scan write. I'm waiting one cycle after the busy flag went low. Shall I wait longer ?

Hi Videoman,

It seems pretty clear that you are losing the clock you are using for reconfig, right when you reconfigure the PLL. There is no guarantee that you keep getting a valid output from a PLL when you reconfigure it -- clocks stop, it loses lock, you might get glitches or runts, you might not get enough clock pulses to completely shift the scan chain into the PLL and it will hang, etc.

Is there any way you can get an independent clock that is not from a quartz crystal ? For instance, maybe add a second PLL to the design that takes 125 MHz down to 72, which is never reconfigured. Some sort of system housekeeping clock that is unrelated to the video of the moment.

The reconfig clock come from a PLL which is not reconfigured and cannot be. This clock does not stop.

Is it possible due to some clock routing problems.

I managed to get the design working on the Eval Board.

But it still hasn't worked with the actual hard. Afetr some chat with other Altera developper I heard that the problem might come from instable PLL Voltage. We are going to measure that.

Did anybody expirience PLL problem dur to bad voltage.

OK, I finally managed to get the PLL reconfig work.

The solution was too use the PLL in non-compensated mode, the reconfigure ok. In source-synchronous mode the PLL crashed immediately after reconfiguration.

Anybody was seen that behaviour, too ?

Hi,

I am experiencing the same problem as you. Can you give me more details on the settings for the PLL to be reconfigured and any importannt settings for the reconfigure block.

Thanks in advance

Hakim