PLL Reconfiguration problem on Cyclone3

The best way (in my opinion) to dynamically reconfigure a pll is to use the "altpll_reconf" megafunction.

I feed my pll with a 24MHz clock and the "reconf" block with a 6MHz clock. I also use ROMs ("altsyncram") to store the data to reconfigure the pll. The "altpll_reconf" create "pll_scanclk" which is used to feed the ROMs. Pulse, one pll_scanclk cycle, on "write_from_rom", wait enough time, then pulse on reconfig, one pll_scanclk cycle again.

It works for me with clk from external signals or from another pll.

Second thing, make sure your design is clean. When you copy a folder with a design inside, quartus do a lot of bad links. So make sure that all your .vhd are well linked, that there are no problem with the "inst&&&" etc... This could make several strange effects. for example, one of my design mixed the output of my pll after reconfig, and make a cleaned project solved the problem.

good luck!