Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

PLL Reconfiguration problem on Cyclone3

In our design I have to reconfigure a PLL when we change from SD to HD video mode and back. (27 and 74.25 MHz input, and different output clocks.) For some reason clock stopped working and the onl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I'm not quite following your question. What clock were you using as the reconfig clock before? You certainly can't use one of the pll's outputs as the reconfig clock.

Also remember that the maximum scanclk frequency is 100MHz and I expect that's a best case scenario and may be lower for slower speed grades.

Typically I've provided a 50MHz clock from a seperate PLL as the reconfiguration clock.

Jake